The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process provides benefits by increasing production efficiency and lowering associated costs. However, it has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
Semiconductor devices are fabricated by creating a sequence of patterned layers defining semiconductor device features. Lithographic techniques are critical to providing these features and thus to semiconductor manufacturing generally. In a typical lithography process, a photosensitive layer (resist) is applied to a surface of a semiconductor substrate, and an image of features defining parts of the semiconductor device is provided on the layer by exposing the layer to a pattern of radiation. The photosensitive layer is then stripped from the substrate. Currently employed processes such as application of stripping by spray/spin on methods and/or batch methods can be insufficient in some ways. For example, as semiconductor processes evolve to provide for smaller critical dimensions, and devices reduce in size and increase in complexity leading to high aspect ratio features, it is difficult to strip all residue of the photosensitive material from such high-aspect ratio features. As another example, the stripping solution contacts each and every portion of the substrate during the typical processes and thus can attack or damage other features disposed on the substrate. Thus, while the present methods for stripping a material such as a photosensitive material from a substrate may be suitable in some respects, improvements may be desired.